Hi @Kacper_J,
Thank you for trying the software. For a Silicon simulation, 100mV is what I think would be a very large voltage step. For SiC simulation I am not sure how the situation would be much different.
Please try smaller steps, such as 0.005, 0.010, or 0.025 to see if that improves the how far you get in your simulation.
There is a ramp_bias function, which is catches convergence failure, and attempts to reduce the voltage step. It is used in some of the devsim examples, that I should be able to help you with further if the previous experiments helps in your bias sweep.
I am curious about your use of CreateSiliconOxideInterface. Once you switch to the Drift Diffusion Simulation, you would need to make sure that the interface equations are handled properly for electrons and holes.
Please consider CreateSiliconSiliconInterface function as an example showing how to allow Electrons and Holes to flow across the material interface in your example.
Alternatively, you may want to consider using a single region for both the p and n doped areas of the device. Then you can control the doping profile just using step or other function.